1. Field of the Invention
The invention relates to a method of obtaining a structure on a semiconductor wafer by etching through structures defined by an etch mask using a plasma.
2. Description of the Related Art
In semiconductor plasma etching applications, a plasma etcher is usually used to transfer a photoresist mask pattern into a circuit and line pattern of a desired thin film and/or filmstack (conductors or dielectric insulators) on a Si wafer. This is achieved by etching away the films (and filmstacks) underneath the photoresist materials in the opened areas of the mask pattern. This etching reaction is initiated by the chemically active species and electrically charged particles (ions) generated by exciting an electric discharge in a reactant mixture contained in a vacuum enclosure also referred to as a reactor chamber. Additionally, the ions are also accelerated towards the wafer materials through an electric field created between the gas mixture and the wafer materials, generating a directional removal of the etching materials along the direction of the ion trajectory in a manner referred to as anisotropic etching. At the finish of the etching sequence, the masking materials are removed by stripping it away, leaving in its place replica of the lateral pattern of the original intended mask patterns. This etching method is illustrated in FIGS. 1A–C. In this method, a plasma etching process is used to transfer directly the photoresist mask pattern 104 into that of the underlying oxide dielectric thin film 108, as shown in FIG. 1A. The etching generates a contact hole 112 and erodes and damages the photoresist 104, as shown in FIG. 1B. The photoresist is then removed leaving the contact hole 112 in the oxide 108, as shown in FIG. 1C. During the etching process, the mask materials are usually eroded and/or damaged in exchange for the pattern transfer. Consequently, some of the damage and erosion also may be transferred to the underlying layers leaving such undesirable pattern distortions such as striation, CD enlargement, etc.
The objective of the etching methodology, therefore, includes reducing the photoresist mask erosion to enhance the fidelity of the pattern transfer from the photoresist mask patterns. For this purpose, it has been proposed to include a passivation gas in the reactive etching mixture. This passivation gas can be chosen in such a way that its presence selectively reduces the etching damage and erosion of the masking materials relative to the removal rate of the thin film materials to be etched. The passivation gas can be chosen in such a way that, an etching retardation coating is generated on the surface of the masking materials acting as a barrier to slow down the etching reaction. By design, the passivation gas is chosen in a way that it additionally beneficially forms an etching retardation coating on vertical surfaces of the film structures to be etched, such that etching reaction cannot advance in the absence of the ion bombardment. By the nature of the vertical trajectory of the charged particles, etching can therefore advance only in the vertical direction, with little to no etching in the lateral direction, creating an anisotropic etching profile. Hence, the presence of a passivation gas in the etching mixture is very important for the advantage of better etching mask protection and highly anisotropic etching profile by the use of relatively high energy directional ion bombardment.
It has already been proposed that the reactive gas mixture contain etching gases and polymer formers, with the latter acting the role of a passivation gas. In this case, the etching gases release highly reactive species by the excitation of an electrical discharge, which in turn etches the thin film materials to be etched as well as the masking materials by the mechanism of a spontaneous reaction. By the nature of spontaneous reactions, the etching reaction advances in both the vertical as well as the lateral surfaces, creating isotropic etching profiles. The co-presence of a polymer former, through generation of a polymer deposit on the surface of the etching structures and masking materials, can be used to create simultaneously high etching selectivity to masking materials and etching anisotropy, in conjunction with the ion bombardment.
It also has already been proposed that the reactive gas mixture contain polymer former gases and an etching enabler gas. The role of the etching enabler gas is to enable the polymer former gas to release highly reactive species by reacting with the polymer former gases in the presence of an electrical discharge. Alternatively, a retardation coating on the etching materials as well as the masking materials can also be formed by chemical reaction of a properly chosen passivation gas directly with the surfaces of these materials.
A common disadvantage of the above mentioned methods is that the optimum conditions for different aspects of the etching requirement usually do not coincide and by mixing the gases some of the unique properties of each precursor gases may be lost due to inter-reactions. The etching condition optimization almost always involve complex trade-offs into a single etching condition that may not be the optimum should the different etching chemistries be separate.
A variant of the etching methodology is taught in U.S. Pat. No. 5,501,893, issued Mar. 26, 1996 to Laermer et al., entitled “Method of Anisotropically Etching Silicon”. This method separates out the etching gases and polymer former gases into two different steps, each consisting purely of one type of chemicals but not the other. This allows for fast etching rate at low ion bombardment energies, since at low ion bombardment energies, high selectivities to masking materials can be achieved for certain spontaneous etching reactions if the activation energy is slightly lower for the reaction at the surface of the etching materials than the masking materials. By removing the polymer former from the etching process, on the other hand, the etching process would necessarily be isotropic during the duration when the etching is proceeding, since there is no retardation layer to prevent the lateral etching from occurring. Additionally, without the passivation gas in the etching mixture, it would be difficult to obtain sufficient etching selectivity to the masking materials if the desire is there to use higher ion energies. Many etching applications can benefit from high ion bombardment energy to obtain high aspect ratio structures in very small dimension structures, for example.
Additional proposed methods include a stacked masking scheme to improve the overall etching resistance of the masking materials. This is illustrated in FIGS. 2A–F. In FIG. 2A an oxide layer 204 is provided. FIG. 2B shows a hardmask layer 208 placed over the oxide layer. A photoresist mask 212 is placed over the hardmask layer 208, as shown in FIG. 2C. The photoresist mask 212 is used to pattern the hardmask layer 208 to create a patterned hardmask layer 214, and the photoresist layer 212 may be removed, as shown in FIG. 2D. A contact hole 216 is etched in the oxide layer 204, using the patterned hardmask layer 214 as a mask as shown in FIG. 2E. The hardmask is then removed leaving the contact 216 in the oxide layer 204, as shown in FIG. 2F.
The advantages of this method are that, by having a more inert hardmask from which to transfer patterns (circuits and lines) to the underlying films, the etch performance is much enhanced and the requirement on the etching and photolithography is also much reduced. The disadvantages of this method are that, by introducing new process steps and new tool sets into the process flow, it is of higher cost and lower overall throughput. In addition, the extra process complexity also introduces difficulties by itself. For example, the Si hardmask used for dielectric contact etch applications is not as easily stripped as the photoresist mask.
In addition to transfer without lateral CD loss or damage the mask pattern into the etch layer, the lateral CD of a lateral pattern already present in the etch layer may also need to be preserved in many etching applications during the process of etching the etch layer. These etch layer patterns are usually not protected by the etching mask materials. A discussion of this class of etching applications is given using the example of a formation of a dual damascene structure by plasma etching.
To facilitate discussion, FIG. 9A is a cross-sectional view of a stack 900 on a wafer 110 used in the dual damascene process of the prior art. A contact 904 may be placed in a dielectric layer 908 over a wafer 910. A barrier layer 912, which may be of silicon nitride or silicon carbide, may be placed over the contact 904 to prevent the copper diffusion. A via level silicon oxide dielectric layer 916 may be placed over the barrier layer 912. A trench stop layer 920 (silicon carbide or silicon nitride) may be placed over via level dielectric 916. A trench level silicon oxide dielectric layer 924 may be placed over the trench stop layer 920. An antireflective layer (ARL) 928 may be placed over the trench dielectric layer 924. A patterned resist layer 932 may be placed over the ARL 928. The ARL 928 may be formed from silicon nitride, SiON, or other material with a high refractive index and high extinction coefficient.
FIG. 10 is a high level flow chart of a process used in the prior art to form the stack 900 into a dual damascene structure. The stack 900 may be subjected to an etch, which etches a via 940 down to the barrier layer 912 (step 1004). The etching of the via 940 may form a crust 944, which forms sidewalls. The crust 944 and resist 932 may be removed and subsequently repatterned with a new resist layer 960, which is patterned to form a trench (step 1008), as shown in FIG. 9C. The stack may be subjected to an etch, which etches a trench 964 down to the intermediate trench etch stop layer 920 (step 1012), as shown in FIG. 9D. The etching of the trench 964 may cause part of the via level dielectric layer 916 to facet 972. This faceting may be considered as damage to the dual damascene structure. The intermediate trench etch stop layer 920 may be used to reduce faceting. The etching of the trench 964 may also form a new crust 968, which forms sidewalls. The resist layer 160 and crust may then be stripped (step 1016). The stack 900 may then be subjected to a barrier layer etch (step 1020), which opens the via 940 to the copper contact 904, to provide the structure shown in FIG. 9E. A metal barrier layer 974 may be deposited over the copper contact (step 1024), as shown in FIG. 9F. A copper seed layer 976 may then be used to coat the interior of the via and trench. Electroplating may be used to fill the trench and via with copper 978, which is polished down to the trench dielectric layer 924. The copper 978 may be used as a copper connect for the next level, so the process is repeated creating multiple levels of copper connects and dielectric layers.
Although the intermediate trench etch stop layer may be used to reduce faceting, providing and etching the intermediate trench etch stop layer requires additional processing steps, which increases processing time and costs.
In addition, integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. A number of promising materials, which are sometimes referred to as “low-k materials,” have been developed. In the specification and claims, low-k materials are defined as materials with a dielectric constant k that is less than 4. Fluorosilicate glass is one example of a low-k dielectric, which has a dielectric constant of about 3.7. This composes an about 7–9% fluorine doped into SiO2.
Another interesting class of low-k materials is compounds including organosilicate glass, or OSG. By way of example, but not limitation, such organosilicate dielectrics include CORAL™ from Novellus of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; Aurora™ available from ASM International N.V., The Netherlands; Sumika Film® available from Sumitomo Chemical America, Inc., Santa Clara, Calif., and HOSP™ from Allied Signal of Morristown, N.J. Organosilicate glass materials have carbon and hydrogen atoms incorporated into the silicon dioxide lattice which lowers the density, and hence the dielectric constant of the material. A dielectric constant for such films is typically<3.0.
To facilitate discussion, FIG. 11A is a cross-sectional view of part of a wafer in the production of a damascene structure without a trench stop layer and using a low-k dielectric. A contact 1104 may be placed in a low-k dielectric layer 1108 over a wafer 1110. A second contact 1106 may also be in the low-k dielectric layer 1108. A dielectric barrier layer 1112, typically, but not limited to, silicon nitride or silicon carbide, may be placed over the contact 1104 to prevent copper diffusion. A low-k dielectric layer 1120 may be placed over the barrier layer 1112. An antireflective layer (ARL) 1128 may be placed over the low-k dielectric layer 1120. A patterned resist layer 1132 may be placed over the ARL 1128. The patterned resist layer 1132 is patterned to provide a via 1140, which is etched into the low-k dielectric layer 1120. The resist layer 1132 is removed and a second patterned resist layer 1160 is placed over the ARL 1128, as shown in FIG. 11B. The second resist layer 1160 is patterned to provide a trench 1164, which is etched into the low-k dielectric layer 1120.
Because of the absence of the intermediate trench etch stop layer and the use of a low-k dielectric, faceting 1172 in this example may be increased. Such faceting may cause the copper, which would be used to fill in the via and trench, to be too close to the second contact 1106. This may also increase the dimension of the bottom of the via.
To facilitate understanding, FIG. 12A is a cross-sectional view of part of a wafer in the production of a damascene structure without a trench stop layer and using a low-k dielectric. A first contact 1204 and a second contact 1206 may be placed in a low-k dielectric layer 1208 over a wafer 1210. A dielectric barrier layer 1212, typically, but not limited to silicon nitride or silicon carbide, may be placed over the first and second contacts 1204, 1206 to prevent the copper diffusion. A low-k dielectric layer 1220 may be placed over the barrier layer 1212. First 1240 and second 1244 vias may be etched into the low-k dielectric layer 1220. A bottom antireflective coating (BARC) layer 1228 may be spun over the low-k dielectric layer 1220. Such a spun on BARC tends to at least partially fill the vias 1240, 1244 and form sidewalls and plugs in the vias. Generally, thinner vias are filled with BARC to a higher depth than wider vias are filled. Also, more spread apart vias may be filled higher than more closely packed vias. As a result, it may be difficult to have the vias filled to a uniform height.
FIG. 12B is a cross-sectional view of part of the wafer after trenches 1248, 1252 have been etched. The presence of BARC in the vias creates fences 1256, 1260 and, in addition, faceting 1262, 1264. The amount of faceting and the size of the fences are dependent on the height of the BARC. Therefore, non-uniform BARC height may cause non-uniform faceting and fences. The fences may be a stress location, which may cause electro-migration, voids and other failures, which may diminish the reliability of the resulting semiconductor devices.
In addition, plug filling and stripping adds additional costs and complexity to the process flow. In addition, such plugs may cause dielectric poisoning in upcoming dielectric materials. Without plug fillings it may be difficult to prevent and increase in CD of via holes due to erosion by mechanisms, such as faceting. The purpose of this invention is to provide a generic method for etching a feature in a layer or a stack of layers to obtain a high fidelity replica of a lateral pattern formed by a masking material with simultaneously high etching anisotropy and high selectivity to the masking materials as well as to the stop layers. Additionally, this invention intends to provide a generic method for etching a lateral pattern already present in the etch layer that is not covered by the etching mask and not protected or insufficiently protected by a sacrificial filler material, without unduly lateral CD loss and damage to the etch layer lateral patterns.